1. Field
The application relates to a semiconductor memory having dynamic memory cells, and a memory controller and a system accessing the semiconductor memory.
2. Description of the Related Art
In recent years, pseudo SRAMs are increasingly mounted on portable equipments such as mobile phones. The pseudo SRAM is a semiconductor memory having memory cells of a DRAM (dynamic memory cells) and internally and automatically executes a refresh operation of the memory cells to operate as a SRAM. The pseudo SRAM executes the refresh operation without a controller such as a CPU recognizing it, during a period in which a read operation or a write operation is not executed. The refresh operation is executed in response to an internal refresh request periodically generated in the pseudo SRAM.
In a semiconductor memory of this type, when the internal refresh request conflicts with an external access request, one of the refresh operation and an access operation is executed first and thereafter the other of the refresh operation and the access operation is executed. In order to prevent the refresh operation from being recognized by an external part, a refresh operation time taken to execute a refresh operation once is included in an external access cycle time, for instance. In this method, the external access time becomes long, resulting in lowered access efficiency.
With the object to execute the refresh operation without an external part recognizing it and without any deterioration in access efficiency, there has been proposed a semiconductor memory storing a parity code together with write data (for example, Japanese Laid-open Patent Publication No. 2003-173676). In this semiconductor memory, the use of the parity code makes it possible to regenerate read data without reading data from a memory block in which the refresh operation is underway. Further, since an external access request and an internal refresh operation do not conflict with each other, there is no need to include the refresh operation time in the access cycle time. This prevents an increase in the external access time, resulting in improved access efficiency.
However, the use of the parity code necessitates a memory block for storing the parity code, a parity generation circuit, an error correction circuit, and so on. This increases a circuit scale to greatly increase a chip size of the semiconductor memory.